DFT Engineer

Job Description

This role focuses on Design for Testability (DFT) techniques to improve chip testing, fault detection, and reliability in semiconductor development. It involves working with ASIC design and validation flows.

Role Details

• Role: ASIC / RTL / Logic Design Engineer (DFT)
• Industry: Electronic Components / Semiconductors
• Employment Type: Full Time, Permanent
• Department: Hardware & Networks Engineering

Key Responsibilities

Scan Insertion Implementation
Implement scan insertion techniques to enhance test coverage.

ATPG Development
Develop and execute Automatic Test Pattern Generation plans for better fault detection.

BIST Architecture Design
Design Built-In Self-Test architectures to improve chip testing.

DFT Integration
Collaborate with design teams to integrate DFT strategies into development workflows.

Test Analysis
Analyze test results and recommend improvements.

Standards Compliance
Ensure adherence to semiconductor testing best practices.

Required Skills

• VLSI knowledge
• Verilog / VHDL
• Linux environment
• Scan insertion and DFT methodologies
• ATPG and fault analysis
• RTL design knowledge

Good to Have

• SystemVerilog
• Python or scripting
• Perl / Tcl
• Version control tools
• Simulation and synthesis experience

Key Skills

DFT, ASIC, RTL, VLSI, Scan Insertion, ATPG, BIST, Verilog, Linux